The present invention relates to a data processing system having a central processing unit (CPU), a random access memory (RAM), a display device and the like and, more particularly, to a character display system which electronically generates character patterns and displays them on a display device such as a video display (CRT).
One of the prior art character display systems of this type is a CRT display system employing a microprocessor or CPU for the purpose of data transfer control. A display memory for storing all the codes representing characters to be displayed on the CRT screen is sequentially accessed by using addresses delivered from a controller other than the CPU and those codes read out are converted into corresponding video signals representative of character patterns. Such accessing method is called a direct memory access.
For a better understanding of the system, a typical example of the display system which may be assumed within the prior art will be described with reference to FIGS. 1 to 6. FIG. 1, illustrates the display system in block form, which comprises a memory circuit 4 (referred to as a system program ROM) for storing a system operation procedure (program), another memory circuit 3 (as a system program RAM) for temporarily storing data in the course of the system operation, a memory circuit 9 (as a character store RAM) for storing codes of characters to be displayed on the CRT screen, a further memory circuit 10 (as a character pattern generator ROM) for storing character patterns, and a central processing unit 1 (a CPU) for processing data or information relating to those circuit operations and controlling those circuits. The display system further comprises a clock signal generating circuit 2 for generating clock signals .phi.1 and .phi.2 for transfer to the CPU, a display timing signal generating circuit 7 for generating a display timing signal .tau. to display a character pattern on the CRT screen, an address switching circuit 8 for interchangingly switching an address signal .alpha. delivered from the CPU with the display timing signal .tau. from the timing circuit 7, a parallel-to-serial converting circuit 11 for converting parallel bit signals transferred from the character pattern generator ROM 10 into serial bit signals to produce a video signal at an output terminal 12, and an input/output interface circuit 5 coupling a keyboard 6 with the CPU 1. The video signal appearing at the output terminal 12 is applied to a CRT 18 as shown in FIG. 2A, where a corresponding character pattern is visually displayed on the screen of the CRT 18. The character store RAM 9 illustrated in detail in FIG. 2B includes an 8-bit address decoder 19 having address input terminals 21 for decoding an address signal transferred through an address bus 14 and a data store portion 20 for storing data transferred through a data bus 13. The data store portion 20 has data input terminals 22A and data output terminals 22B. The character display locations on the screen of the CRT 18 respectively correspond in one-to-one relation to the memory addresses in the memory portion 20 of character store RAM 9. For example, the memory portion 20 stores at its address 1 a character "A" to be displayed on the upper left side of the screen, and stores at its address 2 a character "B" to be displayed on the upper middle location of the screen. If the CRT screen displays characters over 16 lines each line including 32 characters, the character store RAM 9 needs a memory capacity of 512 bytes (=32.times.16), if one byte is assigned to one character.
The operation of the display system thus constructed will be described for example, when an input signal keyed in from the keyboard 6 is displayed on the CRT screen. There has been known a so-called .phi.2 cycle steal display system by which characters can be constantly displayed on the screen of the CRT 18.
Such a cycle steal display system is disclosed in a Japanese periodical "Transistor Technology", May 1977, pp 215 to 217. In the cycle steal display system, after a time T1 from the leading edge of a clock pulse .phi.1, the CPU 1 produces an address signal .alpha. and transfer of a data signal d is rendered effective through the data bus 13 at the trailing edge of an inverse clock signal .phi.2, as illustrated in FIG. 3. During a period, or time T2, having no clock signal .phi.2 produced, RAM 9 is separated from the address bus 14 of CPU 1, while data is taken out from RAM 9 by using the display timing signal .tau. delivered from the display timing signal generating circuit 7 and is displayed on the CRT screen. At this time, the data taken out from RAM 9 is applied to a printer (not shown) to be printed out when required.
Assume now that a character "A" is entered from the keyboard 6. A character coded signal representing the chThen, the character coded signal is fetched into the CPU 1 through the system RAM 3 in accordance with a program stored in the system ROM 4. Following this, the CPU 1 produces an address signal representing an address location on the CRT screen where the character "A" is to be displayed, and sends the character coded signal previously fetched through the data bus 13 to the 8-bit data-in terminal 22A of the RAM 9.
The address switching circuit 8 is switched by the clock signal .phi.2 to perform the cycle steal display. As shown in FIG. 4, during a period T3 (at g in FIG. 4) permitting the input of the clock signal .phi.2, the switching circuit 8 is turned to the address bus 14 side. During a period T2 having no input of the clock signal .phi.2, it is switched to the side of the display timing signal generating circuit 7. During the period T3, the character store RAM 9 is connected to the CPU 1 to allow the character coded coded data to be written from the CPU 1 into the character store RAM 9. During the period T2, the character store RAM 9 is connected to the display timing signal generating circuit 7. Accordingly, the character coded signal is read out by the display timing signal .tau.. Therefore, the character coded signal representing the character "A" is stored in the character store RAM 9 during the period T3. Subsequently, when a character "B" is inputted from the keyboard 6, its coded signal is stored in an address adjacent to the address storing the coded signal of "A" in RAM 9 during the period T3, as shown in FIG. 2B. In this manner, the entered character coded signals are sequentially stored in the character store RAM 9.
The character data signals stored in the RAM 9 are then outputted through the 8-bit data-out terminals 22B of the RAM 9 and then are displayed by the CRT in the .phi.2 cycle steal display mode. During the period T2 for which the clock signal .phi.2 is not applied to the address switching circuit 8, as shown by h in FIG. 4, the character store RAM 9 is coupled with the display timing signal generating circuit 7 so that the display timing signal .tau. from the display timing signal generating circuit 7 is applied to the address input terminals 21 (FIG. 2B) of the RAM 9. As a result, the character coded signal derived from the character store RAM 9 is outputted to the data input terminals 22B, in synchronism with the horizontal scanning operation. In the present specification, the timing signal generating circuit 7 and the parallel-to-serial converting circuit 11 will be referred to generally as a character drive circuit whose function is known in the art. In the example shown in FIGS. 2A and 2B, the character coded signals of "A", "B" and "C" are outputted from the data output terminals 22B one by one for each period T4 (=T2+T3) during one horizontal scanning period. The output signal from the terminals 22B is applied as a part of an address input signal for the character (pattern) generator ROM 10 to address input terminals 25 (FIG. 5) of the ROM 10, where it selects a signal representing a character "A", "B" or "C" from a character pattern store portion 24, through an address decoder 23. The detail of the character pattern generator ROM 10 is illustrated in FIG. 5 and it forms character patterns, each using 8-bits in a row and 8 bits in a column (64 dots per character). Accordingly, in order to store 64 characters, the memory capacity must be 512 bytes (=64.times.8.times.8).
One character pattern selected from the RAM 9 by the address signal i.e., the character coded signal, is successively outputted to data output terminals 26 once by 8 bits from the top of the character pattern to the bottom by the timing signal from the circuit 7 in synchronism with the horizontal scanning. The 8-bit output signal is converted into a video signal 28 by the parallel-to-serial converting circuit 11 comprising a shift register as shown in FIG. 6 and then is outputted from an output terminal 12 in response to a clock signal 27 generated by the display timing signal circuit 7 and is finally applied to the CRT.
Thus, characters can always be displayed on the screen of CRT 18 by employing the .phi.2 cycle steal display system. That is, the address switching circuit 8 is switched by the clock signal .phi.2 and, during the character display time (referred to as DISP) T4 shown by a reference i in FIG. 4, data is written from CPU 1 into the character store RAM 9 and data is read out therefrom by the display timing signal .tau..
As described above, data of one character is read out from RAM 9 during one period of the clock signal .phi.2. For this, the frequency f.sub..phi. of the clock signal .phi.2 is expressed by the equation (1) EQU f.sub..phi. =(1/K).times.N.times.f.sub.H ( 1)
f.sub.H =horizontal scanning frequency of CRT PA1 N=number of characters on one line PA1 K=effective display range in the horizontal direction of CRT
Therefore, when N is 32 characters, K is 2/3 and f.sub.H is 15.75 KHz, the frequency f.sub..phi. is 756 KHz (=(1/2/3).times.32.times.15.75). .times.15.75).
During one character display time T4, the read/write operation for RAM 9 is performed two times. That is, during that period, access to RAM 9 from CPU 1 and access to RAM 9 from the timing circuit 7 are accomplished. Therefore, the read/write cycle time t.sub.RC of RAM 9 must satisfy the equation (2) ##EQU1## When f.sub..phi. =756 KHz, the read/write cycle time becomes EQU t.sub.RC &lt;661 ns
As in this example, when the CRT specifications have 32 characters per line and an effective display range of 2/3, the CPU and RAM, which are of the type used for general purposes, may be employed. However, such CPU and RAM are not available for the CRT of 80 characters per line. When N is 80 characters per line, K is 2/3 and f.sub.H is 15.75 KHz, the frequency f.sub..phi. of the clock signal .phi.2 and the read/write cycle time t.sub.RC are EQU f.sub..phi. =(1/2/3).times.80.times.15.75=1890 KHz EQU t.sub.RC &lt;1/2f.sub..phi. =265 ns (3)
As seen from the equation (3), a character display system for always displaying characters on the CRT screen with 80 characters per line requires specially designed, expensive circuit components such as a very high-speed operation CPU and character store RAM.
Also in the case of a character display system using a circuit component requiring a refreshing operation such as a dynamic RAM for constantly displaying characters on the CRT screen, the read/write operation is performed two times during one character display time. Accordingly, such a display system needs an expensive and specially designed CPU and RAM.
However, the read time of the general type MOS LSI RAMs commercially available at present is in the order of 300 to 400 ns. Accordingly, when a higher speed RAM is desired, it must be specially designed with high cost. The operating frequency of MOS LSI CPUs currently marketed is at most 1 MHz. As described above, the character display system using clock signals based on the prior art, or using a dynamic RAM requiring refreshing requires an expensive and high-speed RAM and CPU.